1. Field of the Invention
The present invention relates to flash memory technology.
2. Description of Related Art
Flash memory is a class of non-volatile integrated circuit memory technology. The typical flash memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a charge storage structure including a tunnel dielectric layer, the charge storage layer (floating gate or dielectric), and a blocking dielectric layer. According to the early conventional charge trapping memory designs referred to as SONOS devices, the source, drain and channel are formed in a silicon substrate (S), the tunnel dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed of silicon oxide (O), and the gate comprises polysilicon (S). More advanced flash memory technology has been developed, using bandgap engineered tunneling dielectrics in dielectric charge trapping cells. One bandgap engineered cell technology is known as BE-SONOS, as described in Hang-Ting Lue et al., “Scaling Evaluation of BE-SONOS NAND Flash Beyond 20 nm”, 2008 Symposium on VLSI technology, Digest of Papers, June 2008, and in H. T. Lue et al., IEDM Tech. Dig., 2005, pp. 547-550.
These advanced charge trapping memory technologies can have limited endurance and operation speeds, compared to other memory types.
It is desirable to provide technology improving the speed of operation and endurance of flash memory.